1. Field of the Invention
The invention relates to a semiconductor integrated circuit device including an actual circuit and a replica circuit thereof, and more particularly to such a semiconductor integrated circuit device which is capable of detecting a delay error between an actual circuit and a replica circuit and compensating for the detected delay error.
2. Description of the Related Art
In general, a semiconductor integrated circuit device including a delay and phase-synchronization circuit such as DLL (Delay Locked Loop) or PLL (Phase Locked Loop) in order to control phases of input and output timings is designed to further include replica circuits of output and input circuits for controlling delay or phase.
For instance, Japanese Patent Application Publication No. 2001-126474 has suggested such a semiconductor integrated circuit device.
FIG. 1 is a block diagram of a conventional semiconductor integrated circuit device including a delay and phase-synchronization circuit having a replica input circuit and a replica output circuit.
The illustrated semiconductor integrated circuit device is comprised of a first pad 01K to which data is input and from which data and a signal IO1 are output, a second pad 02K to which data is input and from which data and a signal IO2 are output, a first input circuit 03K, a second input circuit 04K, a first output circuit 05K, a second output circuit 06K, and a delay and phase-synchronization circuit 09K.
The first input circuit 03K receives a signal VREF as a reference level signal, amplifies the signal IO1 output from the first pad 01K, and outputs the thus amplified signal as a signal DIN1.
The second input circuit 04K receives a signal VREF as a reference level signal, amplifies the signal IO2 output from the second pad 02K, and outputs the thus amplified signal as a signal DIN2.
The first output circuit 05K receives signals OE and DATA1 as output enable signals, and outputs a signal OUT1 to the first pad 01K as the signal IO1.
The second output circuit 06K receives signals OE and DATA2 as output enable signals, and outputs a signal OUT2 to the second pad 02K as the signal IO2.
The delay and phase-synchronization circuit 09K includes a replica output circuit 07K and a replica input circuit 08K.
The replica output circuit 07K receives a signal DCLK, and outputs a signal ROD.
The replica input circuit 08K receives a signal VREF as a reference level signal, amplifies the signal ROD output from the replica output circuit 07K, and outputs a signal REPD.
The signal DATA1 input into the first output circuit 05K and the signal DATA2 input into the second output circuit 06K are signals delayed by the delay and phase-synchronization signal 09K or synchronized with a signal having a synchronized phase.
FIG. 2 is a circuit diagram of the replica output circuit 07K comprised of delay devices such as an inverter, a buffer and so on, and providing a delay identical to a delay detected in an actual circuit path. The replica input circuit 08K has the same structure as that of the replica output circuit 07K.
The replica output circuit 07K illustrated in FIG. 2 is comprised of a first buffer 01L receiving a signal RIN and outputting a signal RID1, a second buffer 02L receiving the signal RID1 transmitted from the first buffer 01L, and outputting a signal RID2, a third buffer 03L receiving the signal RID2 transmitted from the second buffer 02L, and outputting a signal RID3, and a fourth buffer 04L receiving the signal RID3 transmitted from the third buffer 03L, and outputting a signal ROUT.
The replica output circuit 07K and replica input circuit 08K are necessary to have the same characteristics as those of actual circuits for accomplishing delay and phase synchronization. If characteristics between the replica circuits and the actual circuits are not identical to each other, data output position would be deviated.
However, it is actually unavoidable that an error is caused between a replica circuit and an actual circuit because of differences in a layout, power supply, diffusion conditions, and so on.
Japanese Patent Application Publication No. 10-320976 has suggested a method of adjusting access time in a semiconductor device in which a load in a dummy-load circuit included in a dummy circuit is adjusted in accordance with results of measurement of a frequency and an interface. Specifically, the load of the dummy-load circuit is reduced by a degree corresponding to a half of a maximum variance of access time variable in accordance with a frequency of output data.
Japanese Patent Application Publication No. 2000-163999 has suggested a self-timing control circuit including a variable dummy load having an electrically adjustable capacitor load in place of a dummy load having a fixed capacitor load. Thus, it is possible to optimize a capacitor load of a variable dummy load in a step of testing a wafer of a device.